23ECE302 · VLSI Design · Mock Papers

5 Full Practice Papers

2 Easy, 2 Medium, 1 Hard — each 50 marks across all 6 mid-term topics. No real past-year paper was available, so difficulty and style are calibrated against your faculty's own numericals worksheet and slide examples. Attempt on paper first, then reveal the answer key.

EASY

Mock Paper — Easy, Set 1

Total Marks: 50  ·  Recommended Time: 90 minutes  ·  Covers all 6 mid-term topics

Part A — Conceptual (5 × 2 = 10 marks)

  1. [2] State the pass-transistor rule for an nFET. What voltage appears at the output when it passes logic-1 with VDD=3.3 V, VTn=0.6 V and VG=VDD? Is this a strong or weak level?
  2. [2] List the ordered metal-stack build sequence taught in the lectures (starting from the wafer surface after the active/poly step) and state what a contact connects.
  3. [2] Define the scaling factor S (>1). In one line each, state what happens to (i) channel length L and (ii) supply voltage VDD under full (constant-field) scaling versus constant-voltage scaling.
  4. [2] Write the three IDn region conditions using VGSn, VDSn and VTn (cutoff / triode / saturation) and give the IDn expression for the saturation region (ignore channel-length modulation).
  5. [2] Write the faculty's simplified (η=1) linearised resistance for an nFET, Rn, in terms of βn, VDD and VTn. What are the units of βn?

Part B — Derivations & Design (5 × 6 = 30 marks)

  1. [6] The notes derive the nFET triode current from the differential element dV = IDn·dy / [μn·W·Cox·(VGSn−VTn−V(y))].
    dV = IDn·dy / [μn·W·Cox·(VGSn − VTn − V(y))]
    Starting from this line, integrate y: 0→L and V: 0→VDSn to obtain the triode result. Then show dIDn/dVDSn=0 gives VDS,sat=VGSn−VTn and write the saturation IDn. (All intermediate steps of the integral are set up — you only need to carry out the single integration and the one derivative.)
  2. [6] Design the CMOS gate for Y = (A + B·C)′ using the 6-step PUN/PDN method taught in class (steps 1–6). (a) Write the complement, state how many nFETs/pFETs are needed, (b) draw the NMOS pull-down network (series = AND, parallel = OR) and (c) draw the PMOS pull-up dual (swap series ↔ parallel). Label every transistor gate with A, B or C.
  3. [6] A straight Metal-1 interconnect has sheet resistance Rs=30 Ω/□, width w=0.5 μm and length l=100 μm. (a) Compute the number of squares n=l/w and Rline=Rs·n. (b) If the same trace is bent with 2 corners, each corner square contributes only 0.635× a normal square. Compute the effective neff and the corrected Rline. (c) With Tox=6000 Å, compute Cline=εox·w·l/Tox and τ=Rline·Cline. Use εox=3.9·ε0, ε0=8.854×10−12 F/m.
  4. [6] A process has L=1.0 μm, W=10 μm, tox=100 Å, VDD=5.0 V and VT0n=0.70 V before scaling. Apply scaling factor S=2: fill the after-scaling values for full (constant-field) and constant-voltage scaling for L, W, tox, VDD, VT0, doping NA, Cox, ID and PD/Area, and in one sentence explain why industry moved to full scaling.
  5. [6] For the RC ladder R1=1 kΩ, R2=1 kΩ, R3=1 kΩ with node caps C1=10 fF, C2=10 fF, C3=10 fF (C3 is the load at the far end), write the Elmore delay formula for a ladder and compute TD=R1C1+(R1+R2)C2+(R1+R2+R3)C3. Explain in one line which node contributes the largest R·C product and why.

Part C — Numericals (2 × 5 = 10 marks)

  1. [5] An nFET has k′n=100 μA/V2, W=10 μm, L=1.0 μm, VTn=0.50 V, VSBn=0. (a) Compute βn=k′n·(W/L). (b) With VGSn=2.5 V and VDSn=1.0 V, determine the region (compare VDSn with VDS,sat) and compute IDn. (c) With the same VGSn=2.5 V but VDSn=3.0 V, determine the region and compute IDn. Ignore λ.
  2. [5] The FET RC ladder from Q.B5 (R1=R2=R3=1 kΩ, C1=C2=C3=10 fF) models three series nFETs driving diffusion caps. (a) Compute the Elmore delay TD step by step. (b) If each R is the linearised Rn=1/[βn(VDD−VTn)] of a device with βn=1.0 mA/V2, VDD=3.3 V, VTn=0.6 V, verify that Rn≈370 Ω and comment whether the actual ladder (1 kΩ per stage) is faster or slower than this single-device Rn.
Show Answer Key — Mock Paper — Easy, Set 1

Part A Answers

  1. nFET passes strong 0 (Vy=0) and weak 1. General rule: Vout=Min[Vin, VG−VTn]. With VG=VDD=3.3 V: Vout,max=VG−VTn=3.3−0.6=2.7 V — weak 1 (threshold loss VTn). If Vin < 2.7 V it passes unchanged.
  2. Stack: active (diffusion) + poly gate → contacts opened in Ox1 → Metal-1 → Ox2 (ILD) → Via → Metal-2 (repeat for higher levels). Bottom to top: active → poly → contact → Metal-1 → via → Metal-2. A contact is the vertical connection where metal meets diffusion or poly (different physical levels); required at every metal↔diffusion and metal↔poly junction.
  3. S > 1 is the shrink factor. Full (constant-field): L→L/S and VDD→VDD/S (both shrink, field E=V/L unchanged). Constant-voltage: L→L/S but VDD unchanged (field rises by S). Same for VT0: divides by S under full, unchanged under constant-voltage.
  4. Cutoff: VGSn < VTn → IDn=0
    Triode: VGSn ≥ VTn and VDSn < VGSn−VTn → IDn=k′n(W/L)[(VGSn−VTn)VDSn − VDSn2/2]
    Saturation: VGSn ≥ VTn and VDSn ≥ VGSn−VTn → IDn=(1/2)k′n(W/L)(VGSn−VTn)2
    Saturation boundary VDS,sat=VGSn−VTn.
  5. Rn = 1 / [βn·(VDD − VTn)]   (η=1 simplified form)
    where βn=k′n·(W/L)=μnCox(W/L). Units: A/V2 (often quoted as μA/V2 or mA/V2). With η in 1–6 the general form is Rn=η/[βn(VDD−VTn)].

Part B Answers

  1. Integrate both sides: ∫0VDSn(VGSn−VTn−V)dV = (IDn/(μnW Cox))∫0Ldy. Left = (VGSn−VTn)VDSn−VDSn2/2. So IDn·L/(μnW Cox) = (VGSn−VTn)VDSn−VDSn2/2. With k′n=μnCox and βn=k′nW/L:
    IDn = k′n(W/L)[(VGSn−VTn)VDSn − VDSn2/2] = (βn/2)[2(VGSn−VTn)VDSn − VDSn2]
    Differentiate w.r.t. VDSn: dI/dV = k′n(W/L)[(VGSn−VTn)−VDSn]=0 → VDS,sat=VGSn−VTn. Substituting back gives
    IDn,sat=(βn/2)(VGSn−VTn)2·[1+λ(VDSn−VDS,sat)]
    and without λ, IDn,sat=(βn/2)(VGSn−VTn)2.
  2. Y=(A+B·C)′. (a) Complement Y′=A+B·C. #literals in Y′ = A + B + C = 3 → 3 nFETs and 3 pFETs (always equal). (b) PDN from Y′=A+B·C: OR→parallel, AND→series, so NMOS: A in parallel with (B series C) between output and GND. (c) PUN is the dual: swap series↔parallel → A in series with (B parallel C) between VDD and output, all pFETs with bubble, gates labelled A, B, C (no complement). Truth: when A=1 or (B=C=1) the PDN pulls down → Y=0 as required. Note: AND2/OR2 without complemented inputs would be 6T (gate+inverter); here the AOI is already inverting so no extra inverter.
  3. (a) n = l/w = 100/0.5 = 200 squares. Rline=Rs·n =30×200=6000 Ω. (b) With 2 corners: straight squares =198, corner contribution =2×0.635=1.27, neff=198+1.27=199.27. Rline,corner=30×199.27=≈5978 Ω (≈0.4% lower than straight — corner squares count less). (c) Tox=6000 Å=6000×10−10m=6×10−7m. εox=3.9×8.854×10−12=3.453×10−11 F/m. Cline=εox·w·l/Tox=3.453×10−11×0.5×10−6×100×10−6/6×10−7=3.453×10−11×5×10−11/6×10−7=≈2.88×10−15 F =2.88 fF. τ=R·C=6000×2.88×10−15=≈17.3 ps (≈17.2 ps with corner R). With ε0=8.854×10−14 F/cm the same result is obtained in F/cm units.
  4. ParameterBeforeFull (÷S)Const-V
    L1.0 μm0.50 μm0.50 μm
    W10 μm5.0 μm5.0 μm
    tox100 Å50 Å50 Å
    VDD, VT0n5.0 V, 0.70 V2.5 V, 0.35 V5.0 V, 0.70 V (unchanged)
    NA—×S×S2 (=×4)
    Cox=εox/tox—×S (=×2)×S (=×2)
    ID—÷S (=÷2)×S (=×2)
    PD/Area—unchanged×S3 (=×8)
    W/L unchanged (both ÷S). Industry moved to full scaling because constant-voltage scaling makes power density blow up as S3 and current rise as S while reliability (field) worsens — full scaling keeps power density flat and field constant.
  5. Elmore for a ladder: TD=Σi Ci·(sum of R up to i). So TD=R1C1+(R1+R2)C2+(R1+R2+R3)C3 =1000×10×10−15 +2000×10×10−15 +3000×10×10−15 =10 ps+20 ps+30 ps=60 ps. The farthest node (C3) dominates (30 ps) because it sees the sum of all three resistors — the shared resistance R33=R1+R2+R3 is largest.

Part C Answers

  1. βn=k′n·(W/L)=100 μA/V2×(10/1.0)=1000 μA/V2=1.0 mA/V2. VDS,sat=VGSn−VTn=2.5−0.50=2.0 V.
    (b) VDSn=1.0 V < 2.0 V → triode. IDn=βn[(VGSn−VTn)VDSn−VDSn2/2]=1.0×[2.0×1.0−0.50]=1.50 mA. Using the alternate form (βn/2)[2·2.0·1.0−1.0]=0.5×3.0=1.50 mA.
    (c) VDSn=3.0 V ≥2.0 V → saturation. IDn=(βn/2)(VGSn−VTn)2=0.5×1.0×4.0=2.00 mA (λ=0). If λ were included: ×[1+λ(3.0−2.0)].
  2. (a) TD=R1C1+(R1+R2)C2+(R1+R2+R3)C3=1k·10f+2k·10f+3k·10f=10ps+20ps+30ps=60 ps.
    (b) Rn=1/[βn(VDD−VTn)]=1/[1.0×10−3×(3.3−0.6)]=1/(2.7×10−3)=≈370 Ω (with VDD=3.3 V; with VDD=3.0 V it is 1/(1m×2.4)=417 Ω). The ladder uses 1 kΩ per stage, so it is slower (≈2.7× the single-device Rn) — a wider device (larger W) or shorter L would be needed to hit the 370 Ω target (W=(1/[Rnk′n(VDD−VTn)])·L).
EASY

Mock Paper — Easy, Set 2

Total Marks: 50  ·  Recommended Time: 90 minutes  ·  Covers all 6 mid-term topics

Part A — Conceptual (5 × 2 = 10 marks)

  1. [2] An nFET gate is at VDD=5.0 V, VTn=0.7 V and its source is driven to 3.0 V, 2.0 V and 0 V in three trials. Using Vout=Min[Vin, VG−VTn], state the output for each trial and the clamped maximum.
  2. [2] Explain in one sentence each: (a) why "active = NOT field-oxide" and (b) why there is no separate oxide mask for the gate oxide (self-aligned gate).
  3. [2] Define the threshold voltage VTn in terms of the charge regimes (QB vs QB+Qe) and write the oxide capacitance per unit area Cox=εox/tox with εox=3.9·ε0. What is the unit of Cox?
  4. [2] Under constant-voltage scaling with factor S, how do power per device PD and power density PD/Area scale? Why does this force a move to constant-field (full) scaling?
  5. [2] In the FET RC model the gate capacitance CG=Cox·W·L′ is split as CGS≈CGD≈0.5·CG. Write the total source and drain capacitances CS, CD including junction caps CSB, CDB, and state the formula for a single-sided junction cap as Cbottom+Csidewall with areas.

Part B — Derivations & Design (5 × 6 = 30 marks)

  1. [6] Compare a single nFET pass transistor, a single pFET pass transistor and a transmission gate (TG = nFET ∥ pFET with complementary gates s, s′). For each, state the voltage range it can pass without threshold loss and the weak level if any. Then write the TG-based 2:1 MUX expression F=P0·s′+P1·s and say which TG is on when s=1.
  2. [6] Draw the CMOS schematic for F=(A·B)′ (NAND2) labelling the 2 NMOS (series) and 2 PMOS (parallel) transistors. Then show how to obtain F=A·B (AND2) from it and state the total transistor count (with inverter). Also state the bubble-pushing mnemonic: which operation maps to NMOS series vs parallel?
  3. [6] A Metal-2 trace has Rs=25 Ω/□, w=1.0 μm, l=120 μm, Tox=5000 Å. (a) Compute n=l/w and Rline. (b) Compute Cline=εox·w·l/Tox (use εox=3.9·ε0). (c) Compute τ=Rline·Cline and write v(t)=Vs(1−e−t/τ). If the trace has 1 corner (0.635 factor), recompute neff and the new Rline.
  4. [6] State the body-bias threshold formula VTn=VT0n+γ(√(2|φF|+VSBn)−√(2|φF|)) and the definition of γ. For Na=8×1014 cm−3, tox=120 Å, explain qualitatively whether VTn rises or falls when VSBn is increased from 0 to 2 V and why. No full numeric substitution is required — just the direction and the role of γ.
  5. [6] (a) Derive or state Rn=1/[βn(VDD−VTn)] and compute it for k′n=100 μA/V2, W=10 μm, L=1.0 μm, VDD=3.0 V, VTn=0.50 V. (b) For the same device, compute the actual resistance Ractual=VDSn/IDn when diode-connected (VGSn=VDSn=VDD=2.5 V is used as a check: VDS,sat=2.0 V, IDn,sat=2.0 mA) and comment why the linearised Rn underestimates the true R at this bias.

Part C — Numericals (2 × 5 = 10 marks)

  1. [5] Gate oxide thickness tox=100 Å, μn=500 cm2/V·s, μp=200 cm2/V·s. (a) Compute Cox=εox/tox in F/cm2 and in fF/μm2 (use εox=3.9·ε0, ε0=8.854×10−14 F/cm). (b) Compute the process transconductances k′n=μnCox and k′p=μpCox in μA/V2.
  2. [5] An nFET with W=10 μm, L=1.0 μm, k′n=100 μA/V2, VTn=0.50 V is diode-connected with VGSn=VDSn=VDD=2.5 V. (a) Compute βn and VDS,sat and decide saturation vs triode. (b) Compute IDn (saturation, λ=0). (c) Compute the actual resistance Ractual=VDSn/IDn and the linearised Rn=1/[βn(VDD−VTn)] and state which is larger and by what factor (≈).
Show Answer Key — Mock Paper — Easy, Set 2

Part A Answers

  1. Clamped max = VG−VTn=5.0−0.7=4.3 V. Vout=Min[Vin,4.3]: 3.0 V→3.0 V (below clamp, passed unchanged); 2.0 V→2.0 V; 0 V→0 V (strong 0). Any Vin >4.3 V would clamp to 4.3 V (weak 1). If gate were low, output would be floating/high-Z.
  2. (a) Active = NOT FOX: active area is wherever the thick field oxide (FOX) is absent — the mask defines FOX, its complement is the thin-oxide active region where transistors are built. (b) Self-aligned gate: gate oxide is grown everywhere, then poly is patterned; the poly itself masks the channel during source/drain implantation, and the oxide over source/drain is etched using poly as the mask — so no separate "gate-oxide mask" is needed; oxide remains only under poly.
  3. VTn is the minimum VGSn at which a mobile inversion charge appears. For VG<VTn: QS=QB (only immobile depletion charge); for VG>VTn: QS=QB+Qe with Qe=−Cox(VG−VTn) <0 (free electrons). Boundary between these regimes.
    Cox = εox/tox = 3.9·ε0/tox   [F/cm2 or F/m2]
    Unit: F/cm2 (or F/m2; per unit area). Sometimes quoted as fF/μm2 after ×108 conversion.
  4. Constant-voltage (S): I′D=S·ID, PD=VDD·ID → P′D=S·PD (power per device rises), Area′=Area/S2 → PD/Area scales as ×S3 (blow-up). Full scaling keeps VDD∝1/S so I′D=ID/S and P′D=PD/S2, hence PD/Area unchanged. The S3 blow-up under constant-voltage is why industry adopted full/constant-field scaling.
  5. CG=Cox·W·L′, split: CGS≈CGD≈CG/2 (simple model). Diffusion nodes:
    CS = CGS + CSB ,   CD = CGD + CDB
    Per node: CSB (or CDB) = Cbottom+Csidewall with Cbottom=Cj·Abottom=Cj·X·W and Csidewall=Cjsw·Psw=Cjsw·2(W+X) (include overlap L0 as X+L0 if diffusion extends under poly). Cjsw=Cj·xj.

Part B Answers

  1. nFET: passes [0, VG−VTn], strong 0, weak 1 (loss VTn). pFET: passes [VG+|VTp|, VDD], strong 1, weak 0 (floor |VTp|). TG (n∥p, s and s′ complementary): passes full [0, VDD] with no threshold loss — nFET covers the low side, pFET covers the high side. 2:1 MUX:
    F = P0·s′ + P1·s
    When s=1 (s′=0), TG1 (P1 path, gated by s) is ON and TG0 (P0 path, gated by s′) is OFF, so F=P1.
  2. NAND2 Y=(A·B)′: PDN (NMOS): A series B between Y and GND. PUN (PMOS): A parallel B between VDD and Y (dual). Each gate node drives one NMOS and one PMOS (4 transistors). AND2 Y=A·B = (A·B)′ inverted: add an inverter (1 NMOS + 1 PMOS, 2T) → 6 transistors total. If complemented inputs A′,B′ are already available elsewhere, a direct AND can reuse them with different counts — faculty shows both 6T and 8T tallies depending on whether inverter transistors are counted as new. Mnemonic: "multiplication (AND) → NMOS series, PMOS parallel; addition (OR) → NMOS parallel, PMOS series" (bubble-pushing).
  3. (a) n=l/w=120/1.0=120 squares. Rline=Rs·n=25×120=3000 Ω. (b) Tox=5000 Å=5×10−7m. εox=3.453×10−11 F/m. Cline=εox·w·l/Tox=3.453×10−11×1×10−6×120×10−6/5×10−7=3.453×10−11×1.2×10−4/5×10−7=3.453×10−11×240=≈8.29×10−15 F =8.29 fF. (c) τ=R·C=3000×8.29×10−15=≈24.9 ps. Step response v(t)=Vs(1−e−t/τ). With 1 corner: corner counts as 0.635 instead of 1, so neff=119+0.635=119.635, Rline=25×119.635=≈2991 Ω (slightly lower; with 2 corners neff=118+1.27=119.27, R≈2982 Ω).
  4. VTn=VT0n+γ·(√(2|φF|+VSBn) − √(2|φF|)),   γ=√(2qεSiNa)/Cox   [V1/2]
    with |φF|=(kT/q)ln(Na/ni), ni=1.45×1010 cm−3. As VSBn increases, √(2|φF|+VSBn) grows, so the bracket is positive and grows with VSBn → VTn rises (body effect makes the device harder to turn on). Larger Na or thicker tox (smaller Cox) gives larger γ and a stronger shift; the notes' example: VT0n=0.55 V, γ≈0.057 V1/2, VSBn=2 V → VTn≈0.60 V.
  5. (a) βn=k′n·W/L=100 μA/V2×10/1.0=1000 μA/V2=1.0 mA/V2. Rn=1/[βn(VDD−VTn)]=1/[1.0×10−3×(3.0−0.50)]=1/(2.5×10−3)=400 Ω. (b) For VGSn=VDSn=2.5 V, VTn=0.50 V: VDS,sat=VGSn−VTn=2.0 V. Since VDSn=2.5 V ≥2.0 V → saturation. IDn,sat=(βn/2)(VGSn−VTn)2=0.5×1.0×4.0=2.00 mA. Ractual=VDSn/IDn=2.5/0.002=1250 Ω. Linearised Rn=400 Ω is ≈3.1× smaller than actual — the η=1 linear model is a small-VDS linearisation (point-a on the load line) and underestimates resistance when the device is deep in saturation where the I–V curve has flattened and incremental resistance is higher. Faculty's note: at VDD=5 V the same device gives Rn,lin≈101 Ω vs much larger actual; always call out this mismatch.

Part C Answers

  1. (a) tox=100 Å=100×10−8cm=1.0×10−6cm. εox=3.9×8.854×10−14=3.453×10−13 F/cm. Cox=εox/tox=3.453×10−13/1.0×10−6=3.453×10−7 F/cm2. Convert: 1 cm2=108 μm2, so Cox=3.453×10−15 F/μm2=3.45 fF/μm2 (since 1 fF=10−15F).
    (b) k′n=μnCox=500×3.453×10−7=1.7265×10−4 A/V2=172.7 μA/V2. k′p=μpCox=200×3.453×10−7=6.906×10−5 A/V2=69.1 μA/V2. (With the faculty's μn=550, μp=210 these become 189.9 and 72.5 μA/V2 — same method.)
  2. βn=k′n·W/L=100×10/1.0=1000 μA/V2=1.0 mA/V2. (a) VDS,sat=VGSn−VTn=2.5−0.50=2.0 V. VDSn=2.5 V ≥2.0 V → saturation.
    (b) IDn=(βn/2)(VGSn−VTn)2=0.5×1.0×(2.0)2=0.5×4.0=2.00 mA.
    (c) Ractual=VDSn/IDn=2.5/0.002=1250 Ω. Rn,lin=1/[βn(VDD−VTn)]=1/[1.0×10−3×2.0]=500 Ω (if VDD=2.5 V; with VDD=3.0 V the linearised value is 400 Ω). Ractual is ≈2.5× larger (1250/500=2.5; 1250/400=3.1 with the 3.0 V reference) — linear model underestimates R in saturation, as in numerical 5 of the worksheet.
MEDIUM

Mock Paper — Medium, Set 1

Total Marks: 50  ·  Recommended Time: 90 minutes  ·  Covers all 6 mid-term topics

Part A — Conceptual (5 × 2 = 10 marks)

  1. [2] State the pass-transistor rule for a single nFET and a single pFET. For VDD=5 V, VTn=0.70 V, |VTp|=0.75 V, what voltage appears at the output when (i) an nFET with VG=5 V passes logic-1 (Vin=5 V), and (ii) a pFET with VG=0 V passes logic-0 (Vin=0 V)? Identify which transfer is weak in each case.
  2. [2] List the mask layers required for an n-well CMOS inverter and explain two faculty-stressed distinctions: (a) "active = not FOX" and (b) "gate oxide is self-aligned to poly — no separate oxide mask."
  3. [2] Using the scaling table (factor S > 1), explain why constant-voltage scaling leads to a power-density blow-up of S3 while constant-field (full) scaling keeps power density unchanged. Name the two parameters whose different scaling causes this.
  4. [2] The linearized FET RC model gives Rn = 1 / [βn(VDD − VTn)] (eta=1). For an nFET with W=20 µm, L=0.50 µm, k'n=120 µA/V2, VTn=0.65 V, VDD=5 V, the linearized model predicts Rn ≈ 48 Ω but VDSn/IDn computed from the true saturation current is ≈ 110 Ω. Explain in one paragraph why the linear model underestimates the resistance at this bias.
  5. [2] Sketch (describe) the IDn vs VDSn family of curves for VGSn=VTn+1, VTn+2, VTn+3. Mark the triode-to-saturation boundary and give its equation. What is the shape of IDn vs VGSn at fixed large VDSn?

Part B — Derivations & Design (5 × 6 = 30 marks)

  1. [6] Starting from the differential-element relation dV = IDn·dR with dR = dy / (qµnneW xe) and the channel charge Qe(y)= −Cox[VGSn−VTn−V(y)], derive the nFET drain current in the linear/triode region. Show integration y:0→L, V:0→VDSn and define k'n=µnCox, βn=k'n(W/L). Then obtain the saturation boundary VDSn,sat by dIDn/dVDSn=0 and the saturation current.
    IDn,lin = k'n(W/L)[(VGSn−VTn)VDSn − VDSn2/2] ,   VDSn,sat=VGSn−VTn ,   IDn,sat=(βn/2)(VGSn−VTn)2
  2. [6] Cascaded threshold loss. VDD=5.0 V, VTn=0.70 V. Stage 1: nFET M1 with VG1=VDD passes Vin=VDD. Its output V1 drives the gate of nFET M2 (so VG2=V1). M2 passes Vb=VDD from its drain to its source as Vout. (a) Compute V1 using Vout=Min[Vin, VG−VTn]. (b) Compute Vout=Min[Vb, VG2−VTn]. (c) A third identical nFET M3 is added with its gate tied to VDD and its drain fed by Vout — what is V3? Explain why only the gate-driven stage causes a second VTn drop while a simple series chain does not.
  3. [6] Euler-path stick-diagram construction. The CMOS gate implements F = (A·(B + C) + D·E)' . (a) Write F' in sum-of-products, state the number of NMOS and PMOS transistors, and describe the series/parallel topology of the PDN and PUN (dual networks). (b) Build the PMOS and NMOS graphs (nodes = VDD/GND plus input labels; edges = transistors labeled by gate input) and find a common Euler path. Give the poly-gate order that yields a single diffusion run without a break.
    PMOS graph (VDD) VDD X Y A B C D∥E path via X NMOS graph (GND) GND P Q OUT D E A B—C series Hint: B and C are parallel in PMOS, series in NMOS; D,E swap similarly.
    Euler graphs for F=(A·(B+C)+D·E)′ — find one input order traversing every edge once in both graphs.
  4. [6] Scaling table application. A process is scaled with factor S=1.4. Before scaling: L=0.50 µm, W=10 µm, tox=120 Å, VDD=3.30 V, VT0=0.70 V, NA=8×1014 cm−3, Cox=2.88 fF/µm2, IDn,sat=2.50 mA, P=8.25 mW. Compute the scaled values under (i) constant-field (full) scaling and (ii) constant-voltage scaling for: L, VDD, Cox, IDn,sat, power P, and power density P/Area. State which scaling the industry adopted and why.
  5. [6] Interconnect RC with corners. A serpentine Metal-1 trace has sheet resistance Rs=32 Ω/square. The straight sections total 44 squares and there are 6 corner squares. Each corner square contributes 0.635× a normal square. The trace width is w=1.0 µm, total straight length l=44 µm (so n=l/w checks out), inter-level oxide thickness Tox=6000 Å, εox=3.9ε0, ε0=8.854×10−12 F/m. Compute (a) effective number of squares neff, (b) Rline=Rs·neff, (c) Cline=εoxwl/Tox, (d) τ=RlineCline, and (e) the step-response v(t)=Vs(1−e−t/τ) value at t=τ for Vs=3.3 V.
    Rline=Rs·n ,   Cline=εoxwl/Tox ,   τ=RlineCline

Part C — Numericals (2 × 5 = 10 marks)

  1. [5] Body bias and drain current (nFET). Given tox=120 Å, Na=8×1014 cm−3, VT0n=0.55 V, ε0=8.854×10−14 F/cm, εSi=11.8ε0, εox=3.9ε0, q=1.602×10−19 C, kT/q=0.026 V, ni=1.45×1010 cm−3, µn=520 cm2/V·s, (W/L)=10.
    (a) Compute Cox and γ = sqrt(2qεSiNa)/Cox. (b) Compute |φF|=(kT/q)ln(Na/ni) and VTn at VSBn=2.0 V using VTn=VT0n+γ(sqrt(2|φF|+VSBn)−sqrt(2|φF|)). (c) For VGSn=3.0 V, VDSn=2.5 V, VSBn=2.0 V, determine the operating region and compute IDn.
    Cox=εox/tox ,   γ=sqrt(2qεSiNa)/Cox ,   VTn=VT0n+γ(sqrt(2|φF|+VSBn)−sqrt(2|φF|))
  2. [5] Elmore delay in a 3-stage RC ladder modeling a FET chain. R1=350 Ω, R2=450 Ω, R3=600 Ω (FET linear resistances), C1=22 fF, C2=18 fF, C3=28 fF at the three diffusion nodes, plus a load CL=12 fF at the far end (so the capacitance at node 3 is C3+CL). Compute the Elmore delay TD = R1C1 + (R1+R2)C2 + (R1+R2+R3)(C3+CL). Also give the delay if CL were absent. Which node contributes most and why?
    TD = ∑ Ci·Rii ,   ladder: TD=R1C1+(R1+R2)C2+(R1+R2+R3)(C3+CL)
Show Answer Key — Mock Paper — Medium, Set 1

Part A Answers

  1. nFET: strong 0 (Vout=0), weak 1: Vout=Min[Vin,VG−VTn]. pFET: strong 1 (VDD), weak 0: Vout=Max[VG+|VTp|,Vin]. (i) nFET passing 5 V with VG=5 V: Vout=5−0.70=4.30 V (weak 1, threshold loss). (ii) pFET passing 0 V with VG=0 V: Vout=0+0.75=0.75 V (weak 0). Design rule: use pFET for 1, nFET for 0.
  2. Visible: p-substrate, n-well, n+/p+ diffusion, gate oxide, poly gate. Masks: n-well mask, active (= NOT field oxide), n+ mask, p+ mask, poly mask. (a) Active is defined as wherever thick field oxide (FOX) is absent — not a deposited layer itself. (b) Thin gate oxide is grown everywhere then poly is patterned; oxide not covered by poly is etched away, so the remaining oxide is automatically aligned to the poly edge — no extra mask needed. Metal1/ via /Metal2 via Ox1/Ox2 stack on top.
  3. Full scaling: V, L, tox all /S, so P=VI scales as (1/S)(1/S)=1/S2 and Area scales 1/S2, hence P/Area unchanged. Constant-voltage: V unchanged while I scales ×S (narrower device, same V), so P scales ×S and Area 1/S2 gives P/Area ×S3 blow-up. The two culprits are VDD (divided by S vs unchanged) and doping NA (×S vs ×S2). Industry adopted full/constant-field scaling to avoid thermal runaway.
  4. Actual resistance uses VDSn/IDn on the true nonlinear I−V curve at VDSn=VGSn=VDD=5 V (pinch-off/saturation point where I has flattened to (β/2)(VDD−VTn)2). The linearized eta=1 model is Rn≈1/(β(VDD−VTn)) which is the small-VDS (triode) slope resistance at point “a” — i.e. the tangent at the origin, much steeper (lower R). At large VDS the current barely increases, so V/I is larger. Faculty trap: linear R underestimates actual large-signal R by >2× here (47.9 vs 110 Ω).
  5. Each IDn−VDSn curve rises as (β)[(VGSn−VTn)VDSn−VDSn2/2] then flattens at VDSn,sat=VGSn−VTn to a horizontal saturation current (β/2)(VGSn−VTn)2. The locus of the knees is the parabola VDSn=VGSn−VTn (dashed across the family). IDn vs VGSn (at fixed VDSn > saturation): zero for VGSn<VTn, then quadratic ∝(VGSn−VTn)2.

Part B Answers

  1. Qe(y)=−Cox(VGSn−VTn−V(y)). dR=dy/(qµnneW xe), and Qe=−q nexe so dV=IDndy/(µnW(−Qe))=IDndy/[µnW Cox(VGSn−VTn−V)]. Rearranged: IDndy=µnW Cox(VGSn−VTn−V)dV. Integrate 0→L, 0→VDSn: IDnL=µnW Cox[(VGSn−VTn)VDSn−VDSn2/2]. Hence IDn,lin=k'n(W/L)[(VGSn−VTn)VDSn−VDSn2/2]. Set dI/dVDSn=k'n(W/L)[(VGSn−VTn)−VDSn]=0 ⇒ VDSn,sat=VGSn−VTn. Substituting gives IDn,sat=(βn/2)(VGSn−VTn)2 (times [1+λ(VDSn−VDSn,sat)] with CLM).
  2. (a) V1=Min(5.0,5.0−0.70)=4.30 V. (b) VG2=V1=4.30 V, so VG2−VTn=3.60 V. Vout=Min(5.0,3.60)=3.60 V — second threshold drop because the degraded voltage now limits the gate drive. (c) V3=Min(Vout=3.60, VDD−VTn=4.30)=3.60 V (no further drop). A plain series chain with all gates at VDD: Vmax=VDD−VTn at the first device; subsequent devices see VG−VTn=4.30 V which exceeds the already-degraded input (4.30 V), so Min picks the input — no extra loss. Only when the degraded output drives a gate (case b) does VG−VTn shrink and impose a second loss.
  3. (a) F=(A(B+C)+DE)' so F' = A(B+C)+DE = AB+AC+DE. Need 5 NMOS + 5 PMOS = 10 transistors. PDN: A in series with (B||C), that block in parallel with (D in series with E). PUN is dual: A in parallel with (B in series with C), that block in series with (D in parallel with E). (b) One valid common Euler path is A → B → C → D → E (or E,D,C,B,A reversed). Traversal: PMOS graph: VDD—A—X—B—Y—C—? plus D||E branch; NMOS graph: GND—D—P—E—Q—A—OUT with B||C series. Ordering the poly strips B-C adjacent keeps the parallel pair share diffusion without a break; the single diffusion run order A-B-C-D-E (or A-C-B-D-E) traverses both graphs without lifting the pen. Stick diagram: one continuous n-diffusion strip crossed by poly in that order on the bottom, mirror p-diffusion on top with the dual connections; VDD metal contacts at PMOS top, GND at NMOS bottom, output contact at the common drain node. Corner squares in the metal bends count 0.635 each if routed.
  4. S=1.4. Full scaling divides L,W,tox,VDD,VT0 by S; multiplies NA by S and Cox by S. Constant-voltage divides geometry by S but leaves V unchanged and multiplies NA by S2.
    (i) Full: L'=0.50/1.4=0.357 µm, W'=7.14 µm, tox'=85.7 Å, VDD'=3.30/1.4=2.357 V, Cox'=2.88×1.4=4.03 fF/µm2, ID'=2.50/1.4=1.786 mA, P'=8.25/1.42=4.21 mW, P/Area unchanged (1×).
    (ii) Const-V: L'=0.357 µm (same), VDD'=3.30 V (unchanged), Cox'=4.03 fF/µm2 (same), ID'=2.50×1.4=3.50 mA, P'=8.25×1.4=11.55 mW, P/Area'=11.55/(1/1.42)=22.64 mW per old area → ×S3=2.744. Industry chose full/constant-field scaling to keep power density flat; constant-voltage would overheat.
  5. (a) neff = 44 + 6×0.635 = 44 + 3.81 = 47.81 squares. (b) Rline=32×47.81=1530 Ω. (c) εox=3.9×8.854e-12=3.453e-11 F/m, w=1.0µm=1.0e-6 m, l=44µm=44e-6 m, Tox=6000Å=6.0e-7 m. Cline=3.453e-11×1.0e-6×44e-6/6.0e-7 =3.453e-11×73.33e-6=2.53 fF (2.53×10−15 F). (d) τ=1530×2.53e-15=3.87 ps (3.87×10−12 s). If using cm units: εox=3.453e-13 F/cm, w=1e-4 cm, l=44e-4 cm, Tox=6e-5 cm gives same C. (e) v(τ)=3.3(1−e−1)=3.3×0.632=2.09 V. At t=2.3τ ≈ 8.9 ps reaches 90% of Vs.

Part C Answers

  1. (a) tox=120Å=120e-8 cm=1.20e-6 cm. Cox=εox/tox=3.453e-13/1.20e-6=2.878×10−7 F/cm2 = 2.88 fF/µm2. γ=sqrt(2qεSiNa)/Cox. Numerator sqrt(2×1.602e-19×1.045e-12×8e14)=sqrt(2.68e-16)=1.637e-8. /2.878e-7=0.0569 V1/2. (b) |φF|=0.026×ln(8e14/1.45e10)=0.026×10.918=0.2839 V, 2|φF|=0.5677 V. sqrt(2.5677)=1.6024, sqrt(0.5677)=0.7535, diff=0.8489, ×0.0569=0.0483, VTn=0.55+0.0483=0.598 V (≈0.60 V). At VSBn=3 V would be 0.615 V — include as check. (c) VDSn,sat=VGSn−VTn=3.0−0.598=2.402 V. Since VDSn=2.5 > 2.402 → saturation. k'n=µnCox=520×2.878e-7=1.496e-4 A/V2=149.6 µA/V2. βn=k'n(W/L)=149.6×10=1.496 mA/V2. IDn,sat=(βn/2)(2.402)2=0.748e-3×5.770=4.32 mA. If VDSn had been 1.0 V (<VDSn,sat), triode: IDn=1.496e-3×[(1.402)×1 −0.5]=1.35 mA.
  2. TD=R1C1+(R1+R2)C2+(R1+R2+R3)(C3+CL) =350×22e-15 +800×18e-15 +1400×40e-15 =7.70e-12+14.40e-12+56.00e-12=78.1 ps (7.81×10−11 s). Without CL: last term 1400×28e-15=39.20e-12, total =7.70+14.40+39.20=61.3 ps. Node 3 dominates (56 ps / 78 ps ≈ 72%) because its capacitance is largest and it sees the sum of all three resistances (R33=R1+R2+R3). This is the Elmore insight: far-end capacitance is most expensive.
MEDIUM

Mock Paper — Medium, Set 2

Total Marks: 50  ·  Recommended Time: 90 minutes  ·  Covers all 6 mid-term topics

Part A — Conceptual (5 × 2 = 10 marks)

  1. [2] A transmission gate (TG) uses an nFET and pFET in parallel with complementary controls s and s'. Explain why a TG passes the full range [0, VDD] without threshold loss while a single nFET cannot. Give the MUX function F = P0s' + P1s implemented with two TGs.
  2. [2] Define sheet resistance Rs=ρ/t and Rline=Rs·(l/w). A Metal-1 trace has Rs=30 Ω/square, l=60 µm, w=0.60 µm. How many squares is this trace? If the trace has two 90° bends, how does the 0.635 corner-square factor modify the resistance?
  3. [2] The mobility ratio r=µn/µp ≈ 2–3. Why must the PMOS in an inverter be made wider (Wp ≈ r·Wn) for equal rise/fall drive? Give Rp=1/[βp(VDD−|VTp|)] and explain the sizing.
  4. [2] State the aspect-ratio invariance under scaling: what happens to W/L when both W and L are divided by S? What happens to C'ox and k'n under constant-field scaling?
  5. [2] Write the junction-capacitance model C = C0/(1+VR/φ0)mj and explain the three geometry terms: bottom area Cj·X·W, sidewall perimeter Cjsw·2(W+X), and the poly-overlap correction (X+L0). When is mj=1/2 vs 1/3?

Part B — Derivations & Design (5 × 6 = 30 marks)

  1. [6] Derive the body-bias (back-gate) threshold shift from first principles. Starting from γ = sqrt(2qεSiNa)/Cox and |φF|=(kT/q)ln(Na/ni), show that VTn=VT0n+γ(sqrt(2|φF|+VSBn)−sqrt(2|φF|)). Explain physically why a positive VSBn (reverse body bias) increases VTn — more bulk depletion charge must be supported by the gate.
  2. [6] CMOS logic design. Design F(w,x,y,z)=w + x(y+z) in CMOS with minimum transistors. Steps: (i) write F', apply De Morgan to get a sum-of-products suitable for series/parallel mapping (bubble-pushing: AND→NMOS series/PMOS parallel, OR→NMOS parallel/PMOS series), (ii) draw the PDN and PUN schematics, (iii) state total transistor count and explain why AND/OR need an extra inverter stage while NAND/NOR do not.
  3. [6] Euler-path stick diagram. For the function G(A,B,C)=(A+B+A'C')' , (i) minimize or expand to the form that maps to transistors, (ii) build the PMOS and NMOS graphs and find a common Euler path, (iii) describe the stick diagram — single diffusion run, poly order, placement of VDD/GND contacts and output tap. Mention both the straight-strip and compact “+”/cross shared-diffusion notations as equivalent.
    PMOS graph VDD M N A B A' C' NMOS graph GND P OUT A series B parallel A'—C' series
    Euler graphs for G=(A+B+A'C')′ — dual networks; trace one order covering all edges in both graphs.
  4. [6] Scaling — full table. For S=1.5, fill the scaled values for L, W, tox, Xj, VDD, VT0, NA, Cox, ID, P and P/Area under both constant-field and constant-voltage scaling. Before: L=0.60 µm, W=12 µm, tox=100 Å, VDD=5.0 V, NA=5×1014 cm−3, ID=3.0 mA. Show that W/L is invariant and that β'=S·β under full scaling.
  5. [6] Mixed pass-transistor floating node. A node Vx is shared by (top) a pFET with source at VDD=5 V, gate VGp=1.0 V, and (bottom) an nFET with source at GND=0 V, gate VGn=5 V. The pFET drain and nFET drain both connect to Vx. VTn=0.70 V, |VTp|=0.70 V. (a) Determine which terminal of each FET is actually the source (higher voltage for pFET, lower for nFET) assuming Vx starts between the rails. (b) Compute the pFET limit Vx,max-p=VGp+|VTp|? Wait — apply Vout=Max(VG+|VTp|,Vin) and nFET limit Vx,min-n=Min(Vin,VGn−VTn) correctly with the identified source/drain. (c) Will Vx float, be pulled high, or pulled low? What does this imply for the need for a transmission gate or a restoring inverter?

Part C — Numericals (2 × 5 = 10 marks)

  1. [5] Body bias and triode current (nFET). Given tox=100 Å, Na=1.0×1015 cm−3, VT0n=0.52 V, ε0=8.854×10−14 F/cm, εSi=11.8ε0, εox=3.9ε0, q=1.602×10−19 C, kT/q=0.026 V, ni=1.45×1010 cm−3, µn=550 cm2/V·s, (W/L)=8.
    (a) Compute Cox and γ. (b) Compute 2|φF| and VTn at VSBn=1.8 V. (c) For VGSn=2.8 V, VDSn=1.5 V, VSBn=1.8 V, determine the region and compute IDn.
    Cox=εox/tox ,   γ=sqrt(2qεSiNa)/Cox ,   |φF|=(kT/q)ln(Na/ni)
  2. [5] Interconnect RC — serpentine with corners and step response. A Metal-1 serpentine has Rs=32 Ω/square, 200 straight squares and 4 corner squares (each 0.635×), width w=1.0 µm, total length l=200 µm (so n=l/w=200), Tox=6000 Å, εox=3.9ε0, ε0=8.854×10−12 F/m. Compute (a) neff and Rline, (b) Cline=εoxwl/Tox, (c) τ=RlineCline, (d) v(t) at t=τ and t=3τ for a 0→3.3 V step (v(t)=Vs(1−e−t/τ)).
    Rline=Rs·neff ,   neff=nstraight+0.635·ncorners ,   τ=RlineCline
Show Answer Key — Mock Paper — Medium, Set 2

Part A Answers

  1. Single nFET: Vout=Min[Vin,VG−VTn] so a logic-1 loses VTn (weak 1 ≈ VDD−VTn). Single pFET: Vout=Max[VG+|VTp|,Vin] so a logic-0 is lifted to |VTp| (weak 0). TG puts them in parallel: the nFET handles 0 strongly, the pFET handles 1 strongly, so the combination passes the full [0,VDD] with no threshold loss; controls must be complementary (s=1 turns nFET on, s'=0 turns pFET on). MUX: two TGs with gates s/s' and s'/s selecting P0/P1 → F=P0s'+P1s, extendable to 4:1 with s1s0.
  2. Rs=ρ/t (Ω/square). n=l/w=60/0.60=100 squares. Bare R=30×100=3000 Ω ignoring corners. With two bends: neff=100+2×0.635? Wait — if the 60 µm already includes the corner length, the corner squares replace part of the count, so effective addition is 2×0.635 instead of 2×1 → neff=(98+2×0.635)=99.27 → R=2978 Ω (slightly less than straight). If corners are extra bends outside the straight count, neff=100+2×0.635=101.27 → R=3038 Ω. Faculty intent: add 0.635 per corner square, not 1.0 — a corner contributes only 63.5% of a straight square's resistance due to current crowding; always state which counting method you use.
  3. β=µCoxW/L, so R ∝ 1/β ∝ 1/µW. Since µn ≈2–3×µp, βn > βp at equal W, giving lower Rn. To equalize, increase Wp ≈ r·Wn (r=2–3) so βp ≈ βn and Rp=1/[βp(VDD−|VTp|)] ≈ Rn. Inverter sized 2:1 to 3:1 (PMOS wider) gives symmetric thresholds.
  4. W/L: both divided by S → (W/S)/(L/S)=W/L unchanged. Cox=εox/tox; tox'=tox/S → C'ox=S·Cox. k'n=µnCox → k'n'=S·k'n (µ approx constant). Hence β'=k'n'(W'/L')=S·β — transconductance grows by S while voltage falls by S, giving I' = I/S under full scaling (they cancel partly).
  5. C0=CjArea, φ0=(kT/q)ln(NaNd/ni2), mj=1/2 abrupt, 1/3 graded (linearly graded junction). Bottom: Cj·X·W (area of diffusion bottom). Sidewall: Cjsw·2(W+X) where Cjsw=Cjxj (F/cm) along the perimeter; xj is junction depth. Poly overlap: the diffusion extends L0 under the gate edge, so replace X by (X+L0) in the bottom term: CjW(X+L0). Total CSB/CDB=Cbottom+Csidewall; CS=CGS+CSB.

Part B Answers

  1. Bulk charge |QB|=sqrt(2qεSiNaφs). Threshold is when φs=2|φF|+VSBn (surface needs 2φF plus the body bias to invert against a reverse-biased substrate). QB= −Cox(VTn−VT0n) in depletion, so VTn=VT0n+|QB|/Cox=VT0n+[sqrt(2qεSiNa)/Cox](sqrt(2|φF|+VSBn)−sqrt(2|φF|)). Defining γ=sqrt(2qεSiNa)/Cox gives the compact form. Physically, VSBn>0 widens the depletion region ⇒ more fixed acceptor charge ⇒ gate must support more bulk charge before inversion, so VTn rises. Example: Na=1e15, tox=100Å, γ≈0.053 V1/2, VSBn=3V raises VTn by ≈0.06 V.
  2. F=w+x(y+z)=w+xy+xz. F'=(w+xy+xz)' = w'·(xy+xz)' = w'·[(xy)'·(xz)'] = w'·(x'+y')(x'+z') = w'(x'+y'z') after simplification (or keep as w'(x'+y')(x'+z')). Complement for PDN: F' has literals w',x',y',z' — count them for transistor count. Simpler: implement F' as PDN directly: NMOS branch for w? Actually F' = w'·(x'+y'·z') corresponds to NMOS: w' in series with [x' in parallel with (y' series z')]. Apply bubble-pushing: AND→series NMOS / parallel PMOS, OR→parallel NMOS / series PMOS. So PDN: w' series with (x' || (y'—z' series)); PUN dual: w' parallel with (x' series (y'||z') ). If using F complement method: number of transistors = 2×literals in F' = 8 NMOS+8 PMOS? Wait — count unique gate inputs: w,x,y,z each appears once complemented, so 4 NMOS + 4 PMOS = 8 transistors for F' as PDN + dual PUN. F itself is at the output node (CMOS is inverting, so implementing F' as PDN gives F at the output). NAND/NOR are directly inverting (F' is AND/OR), AND/OR need an extra inverter (NAND+INV, NOR+INV) — 6T vs 4T.
  3. G=(A+B+A'C')' ⇒ G' = A+B+A'C'. For NMOS, sum=>parallel, product=>series. So PDN (from G' or from G dual): A||B||(A'—C' series). PUN dual: A series B series (A'||C' parallel). Build graphs: PMOS nodes VDD—A—B—(A'||C')—OUT gives series-parallel dual. One common Euler path: A → B → A' → C' (or C',A',B,A). Check: NMOS graph GND—A—X—B—Y with A'—C' series branch in parallel — the order A-B-A'-C' traverses PMOS VDD-A-M-B-N-(A'/C') sequentially and NMOS GND-A-P plus the A'-C' branch exactly once each. Stick diagram: single horizontal n-diffusion strip under, p-diffusion on top; four vertical poly strips in order A, B, A', C' crossing both diffusions; shared diffusion between A and B (parallel PMOS share source), series connection between A' and C'. Supply rails: Metal VDD contacts at PMOS top source, GND at NMOS bottom; drains common at OUT via metal. Compact “+” notation draws the parallel pair A||B as a cross-shaped merged diffusion to save area — electrically identical to two transistors sharing both source and drain on one strip.
  4. S=1.5. Invariant: W/L=12/0.60=20 stays 20 after (8/0.40).
    ParamBeforeFull (CF)Const-V
    L0.600.40 µm0.40 µm
    W128.00 µm8.00 µm
    tox, Xj100Å66.7 Å66.7 Å
    VDD,VT05.0 V3.33 V5.0 V (unch.)
    NA5e147.5e14 (×S)1.125e15 (×S2)
    Cox3.45 fF/µm25.18 (×S)5.18 (×S)
    ID3.0 mA2.0 mA (/S)4.5 mA (×S)
    P15.0 mW6.67 mW (/S2)22.5 mW (×S)
    P/Area1×1× (unch.)3.375× (×S3)
    β'=S·β because k'n'=S k'n and (W/L)'=W/L, but I' = (β'/2)(V'GS−V'T)2 with V' =V/S gives I'=(βS/2)(V/S)2=I/S (full) vs V unchanged gives I'=(βS/2)V2=S·I (const-V).
  5. (a) Assume Vx ≈ 2–3 V initially. For pFET: source is the higher-voltage terminal ⇒ VDD=5 V is source, Vx is drain (since 5 > Vx). For nFET: source is lower-voltage terminal ⇒ GND=0 V is source, Vx is drain (since 0 < Vx). So both FETs have Vx as their drain. (b) pFET limit: with source at 5 V, gate at 1.0 V, VSGp=4.0 V, the pFET can pull Vx up toward VDD strongly (strong 1): Vx → VDD=5 V if pFET dominates. It cannot pull below VGp+|VTp|=1.0+0.70=1.70 V when source/drain swap — but here source is fixed at VDD. nFET limit with gate 5 V: Vx,min limited? nFET source is GND, gate 5 V, so VGSn=5 V, nFET can pull Vx down toward GND strongly (strong 0): Vx → 0 V if nFET dominates. pFET: Vout=Max(1.70, Vin) with Vin=5 → 5 V; nFET: Vout=Min(0?, actually Vout=Min[Vin,VGn−VTn] but here Vin is drain voltage — steady state is contention: both ON, Vx is determined by the ratio of Rp and Rn voltage divider (both try to drive). (c) With both gates ON, Vx is a ratioed contention node between 0 and 5 V (neither floating nor cleanly high/low) — static crowbar current flows. In proper CMOS, this never happens; the complementary gate should ensure only one conducts. Fix: use a transmission gate or an inverter-driven complementary pair so pFET and nFET are never both strongly ON fighting; or add a restoring inverter/latch at Vx to pull the weak level to the rail.

Part C Answers

  1. (a) tox=100Å=1.00e-6 cm. Cox=3.453e-13/1.00e-6=3.453×10−7 F/cm2=3.45 fF/µm2. γ=sqrt(2×1.602e-19×1.045e-12×1e15)/3.453e-7. Numerator sqrt(3.35e-16)=1.83e-8. γ=0.0530 V1/2. (b) |φF|=0.026×ln(1e15/1.45e10)=0.026×11.142=0.2897 V, 2|φF|=0.5794 V. sqrt(0.5794)=0.7612, sqrt(2.3794)=1.5425, diff=0.7813, ×0.0530=0.0414, VTn=0.52+0.0414=0.561 V. At VSBn=0, VTn=0.52 V; at 3 V, VTn=0.580 V — monotonic rise. (c) VDSn,sat=VGSn−VTn=2.8−0.561=2.239 V. VDSn=1.5 < 2.239 ⇒ triode (linear) region. k'n=µnCox=550×3.453e-7=1.899e-4 A/V2=189.9 µA/V2. βn=k'n(W/L)=189.9×8=1.519 mA/V2. IDn=βn[(VGSn−VTn)VDSn−VDSn2/2]=1.519e-3×[2.239×1.5 −1.125]=1.519e-3×2.2335=3.39 mA. If VDSn=3.0 V (>VDSn,sat), saturation: IDn,sat=(βn/2)(2.239)2=0.7595e-3×5.013=3.81 mA.
  2. (a) neff=200 +4×0.635=200+2.54=202.54 squares. Rline=32×202.54=6481 Ω (6.48 kΩ). (b) εox=3.9×8.854e-12=3.453e-11 F/m, w=1.0µm=1.0e-6 m, l=200µm=200e-6 m, Tox=6000Å=6.0e-7 m. Cline=3.453e-11×1.0e-6×200e-6/6.0e-7=3.453e-11×333.33e-6=11.51 fF (1.151e-14 F). In cm: w=1e-4 cm, l=2e-2 cm, Tox=6e-5 cm, εox=3.453e-13 → same C=11.51 fF. (c) τ=6481×11.51e-15=74.6 ps (7.46e-11 s). (d) Step 0→3.3 V: v(τ)=3.3(1−e−1)=3.3×0.632=2.09 V, v(3τ)=3.3(1−e−3)=3.3×0.950=3.14 V. Time to 90% ≈2.30τ=171.6 ps. Ignoring the 0.635 corner correction would overestimate R by (204−202.54)/202.54 ≈ 0.7% — small here but ≈10% for short traces with many bends, hence faculty tests it.
HARD

Mock Paper — Hard

Total Marks: 50  ·  Recommended Time: 90 minutes  ·  Covers all 6 mid-term topics

Part A — Conceptual (5 × 2 = 10 marks)

  1. [2] An nFET has VG=3.3V, VTn=0.60V. It is used as a pass transistor with Vin=3.3V on its drain. (a) What is Vout on its source using the faculty Min-rule? Is it a strong or weak level? (b) The same nFET now passes Vin=1.0V — what is Vout and why is it not clamped to VG−VTn? Contrast with the pFET Max-rule and the OFF (floating) case.
  2. [2] State the 6-step faculty algorithm for CMOS schematic synthesis. A student claims: "To build the PMOS pull-up, take f, complement every literal, then swap series/parallel." Explain why this is wrong. What is correctly complemented and what is correctly dualized? Illustrate with f=(A·B)' vs f=(A+B)'.
  3. [2] Distinguish Visible Features from Mask Layers for the n-well CMOS process. Why is "active = NOT field-oxide" a conceptual trap, and why does the gate-oxide have no separate mask (self-aligned)? List the metal-stack build order from substrate to Metal2.
  4. [2] For an nFET, define the three I-V regions (cutoff, triode, saturation) with exact conditions on VGSn, VDSn and VDSn,sat. Derive VDSn,sat=VGSn−VTn from dIDn/dVDSn=0 starting from the linear-region current. Sketch the shape of the IDn vs VDSn family for VGSn=VTn+1, VTn+2, VTn+3.
  5. [2] With scaling factor S>1, the table gives Full scaling: PD→PD/S2, PD/Area unchanged; Constant-voltage scaling: PD→S·PD, PD/Area→S3·PD/Area. Explain physically why the S3 power-density blowup occurs under constant-voltage scaling and why the industry had to move to constant-field (full) scaling.

Part B — Derivations & Design (5 × 6 = 30 marks)

  1. [6] Cascaded nFET pass chain with floating-node twist. VDD=3.3V, VTn=0.60V, |VTp|=0.60V. Body effect neglected.
    (a) Three nFETs M1–M3 in series: all gates tied to VDD, M1 drain = Vin=3.3V, M1 source → M2 drain, M2 source → M3 drain, M3 source = Vout. Find Vout after M1, after M2, after M3 using Vout=Min[Vin, VG−VTn]. Why do M2/M3 not add extra threshold drop? (2m)
    (b) Cascaded gate drive: M1 as above gives node A = VG2. M2 has drain = 3.3V, gate = node A, source = Vout2. Compute VG2 then Vout2 for Vin,M2=3.3V and for Vin,M2=0V. (2m)
    (c) Node Vx shared by a pFET (source=VDD=3.3V, gate=3.3V, drain=Vx) and an nFET (source=GND=0V, gate=0V, drain=Vx). First identify each transistor's true source/drain by voltage, then apply the Min/Max rule and state whether Vx is driven or floating. What changes if the pFET gate is 0V instead? (2m)
    NMOS: Vout=Min[Vin, VG−VTn]   PMOS: Vout=Max[VG+|VTp|, Vin]
  2. [6] K-map to CMOS schematic. A 3-input function is defined as f(a,b,c)=Σm(1,2,5,6) + Σd(0,3) where a is MSB. Don't-care minterms 0(000) and 3(011) may be used.
    (a) Minimise f via K-map, show groupings and write the minimal SOP. Why does variable a disappear? (2m)
    (b) From the minimized f, find f' and state the number of literals in f' → number of NMOS and PMOS required (assume complementary inputs a',b',c' available; also state total if inverters must be added). (2m)
    (c) Draw the NMOS PDN directly from f' (AND→series, OR→parallel) and the PMOS PUN as its logical dual (series↔parallel, inputs not complemented). Verify duality. (2m)
  3. [6] Serpentine poly interconnect: straight length l=180µm, width w=0.6µm, with 4 right-angle bends (corner squares). Sheet resistance Rs=32 Ω/□, oxide thickness Tox=7000 Å, εox=3.9·ε0, ε0=8.854×10−12 F/m.
    (a) Compute total number of squares n = l/w + 0.635·ncorner and Rline=Rs·n. Explain the 0.635 factor. (2m)
    (b) Compute Cline=εox·w·l / Tox (parallel-plate) and the RC time constant τ=Rline·Cline. (2m)
    (c) If this line were scaled by full scaling with S=1.5, how would Rline, Cline and τ scale? Derive from first principles (not table lookup). (2m)
    Rline=Rs·n   Cline=εox·w·l / Tox   τ=Rline·Cline
  4. [6] Euler-path stick layout. Design a CMOS complex gate for F=(A·B + C·D)' — an AOI22 gate.
    (a) Write F' and derive the NMOS PDN topology and the PMOS PUN as its dual. State transistor count. (2m)
    (b) Build the two Euler graphs: PMOS graph (nodes=VDD, internal diffusion nodes, edges=pFETs) and NMOS graph (nodes=GND, internal nodes, edges=nFETs) sharing the same edge labels. (2m)
    (c) Find a common Euler path — an input ordering that traverses every edge of both graphs without reuse — and give the poly-gate order for a single-diffusion-run stick diagram. If no common path existed, what layout penalty would you pay? (2m)
    PMOS graph VDD Y1 OUT A B C D NMOS graph OUT GND X1 X2 A B C D find common trail A–B–D–C etc. single diffusion run → no break
    Euler graphs for F=(A·B+C·D)'. PMOS: (A∥B) ser (C∥D) between VDD–OUT; NMOS: (A ser B) ∥ (C ser D) between OUT–GND. A common Euler trail gives the poly order for a compact stick diagram.
  5. [6] Scaling — derive an untabulated quantity. An inverter has before scaling: tox=120 Å, Cox=2.88 fF/µm2, W=9µm, L=0.6µm, k'n=150 µA/V2, VTn=0.60V, VDD=3.3V, S=1.5.
    (a) Compute CG=Cox·W·L, βn=k'n(W/L), Rn=1/[βn(VDD−VTn)] (η=1) before scaling. (2m)
    (b) Under full (constant-field) scaling (all geometries ÷S, voltages ÷S), derive from first principles the factors for C'G/CG, β'n/βn and R'n/Rn. Hence derive τ'=R'n·C'G scaling and compute C'G, R'n, τ', τ'/τ. This τ is not in the table — you must derive it. (2m)
    (c) Repeat the Rn and IDn,sat scaling for constant-voltage scaling (geometries ÷S, voltages unchanged) and explain why PD/Area ∝ S3 follows. (2m)
    Rn=1/[βn(VDD−VTn)]   CG=Cox·W·L   τ=Rn·CG

Part C — Numericals (2 × 5 = 10 marks)

  1. [5] Body-bias chain. An nFET has tox=110 Å, Na=9×1014 cm−3, VT0n=0.50V, W/L=12, μn=530 cm2/V·s. Use εox=3.9·ε0, εSi=11.8·ε0, ε0=8.854×10−14 F/cm, q=1.602×10−19 C, kT/q=0.026V, ni=1.45×1010 cm−3. Body bias VSBn denotes source-to-body voltage.
    (a) Find Cox and body coefficient γ=√(2q·εSi·Na)/Cox. (1.5m)
    (b) Find 2|φF| where |φF|=(kT/q)·ln(Na/ni), and VTn at VSBn=2.0V using VTn=VT0n+γ(√(2|φF|+VSBn)−√(2|φF|)). (1.5m)
    (c) At VSBn=3.0V, with bias VGSn=3.0V, VDSn=2.4V, find the new VTn, VDSn,sat=VGSn−VTn, state triode vs saturation, and compute IDn (k'n=μn·Cox, βn=k'n(W/L)). (2m)
  2. [5] FET RC model vs actual resistance and Elmore delay. An nFET has W=22µm, L=0.45µm, k'n=135 µA/V2, VTn=0.65V, with VGSn=VDSn=VDD=3.3V (diode-connected). η=1 for the linearized model.
    (a) Compute βn=k'n(W/L), VDSn,sat, state saturation vs triode, and find IDn in saturation: IDn=(βn/2)(VGSn−VTn)2. (1.5m)
    (b) Find actual drain-source resistance Rn,actual=VDSn/IDn. (1m)
    (c) Find linearized resistance Rn,lin=1/[βn(VDD−VTn)] (η=1) and compare: which is larger and why does the η=1 model underestimate R at this bias? Mention operating points a/b/c on the load line. (1.5m)
    (d) This Rn,lin now drives an RC ladder of 3 identical stages each with series R=Rn,lin and shunt C=32 fF to GND. Estimate Elmore delay TD=R1C1+(R1+R2)C2+(R1+R2+R3)C3. (1m)
Show Answer Key — Mock Paper — Hard

Part A Answers

  1. nFET Min-rule: Vout=Min[Vin, VG−VTn]. VG−VTn=3.3−0.60=2.70V.

    (a) Vin=3.3V → Vout=Min[3.3,2.7]=2.7V — weak 1 (threshold loss VTn). Range of nFET is [0, VG−VTn].

    (b) Vin=1.0V → Vout=Min[1.0,2.7]=1.0V — unclamped. The cap VG−VTn is an upper bound; if Vin is already below it, the FET passes it unchanged. KVL gives Vout=Vx−VTn only when Vx>VG−VTn; otherwise Vout=Vx. pFET dual: Vout=Max[VG+|VTp|, Vin], range [(VG+|VTp|),VDD]; passes strong 1, weak 0 (|VTp| floor). If VGSn≤VTn (or VSGp≤|VTp|) transistor OFF → floating / high-Z (undefined).

  2. Faculty algorithm: 1 Write f. 2 Find complement f'. 3 #literals in f' = #NMOS = #PMOS transistors. 4 Draw NMOS PDN from f' : AND→series, OR→parallel. 5 Draw PMOS PUN as logical dual of PDN: series↔parallel swapped, inputs not complemented. 6 PUN to VDD, PDN to GND.

    Trap: "complement every literal" is wrong. Only the function is complemented to get f' for the PDN; the PUN is the dual network of the PDN, not another complement. Dual means topology dual, same gate labels.

    NAND2: f=(AB)' → f'=AB → PDN A ser B (GND), PUN A par B (VDD). NOR2: f=(A+B)' → f'=A+B → PDN A par B, PUN A ser B. If you complemented literals you'd get (A' par B') for NAND's PUN — incorrect; correct is (A par B) with pFETs.

  3. Visible features: p-substrate, n-well, n+/p+ diffusion, gate oxide, poly gate. Mask layers: n-well mask, active mask, n+ mask, p+ mask, poly mask.

    "Active = NOT field-oxide (FOX)": active area is wherever FOX is absent; FOX is the thick isolation oxide, so active is its complement — trap is thinking active is an extra deposited layer. Gate oxide is self-aligned to poly — no separate oxide mask; the poly itself shadows the channel implant/oxidation.

    Stack order bottom→top: active diffusion → poly gate → contact openings in Ox1 → Metal1 → Ox2 (ILD) → Via → Metal2 (repeat for higher metals). Contacts required wherever metal meets diffusion/poly.

  4. Conditions (Vt=VTn):

    Cutoff: VGSn < Vt → IDn=0 Triode: VGSn ≥ Vt and VDSn < VGSn−Vt → IDn=k'n(W/L)[(VGSn−Vt)VDSn−VDSn2/2] Saturation: VGSn ≥ Vt and VDSn ≥ VGSn−Vt → IDn=(βn/2)(VGSn−Vt)2 (βn=k'nW/L)

    Derive VDSn,sat: IDn(VDSn) in triode is parabolic; dIDn/dVDSn=βn[(VGSn−Vt)−VDSn]=0 → VDSn,sat=VGSn−VTn. IDn vs VDSn family: each VGSn curve rises linearly then quadratically in triode, then flat in saturation; dashed parabola VDSn=VGSn−VTn separates regions. IDn vs VGSn: zero until VTn, then quadratic.

  5. Full scaling (÷S): geometries ÷S, voltages ÷S, doping ×S. Current ID ∝ (W/L)·Cox·(V)2 → I'D=ID/S. Power P=I·V → P'=P/S2. Area A∝W·L → A'=A/S2. So P'/A'=(P/S2)/(A/S2)=P/A — constant.

    Constant-voltage scaling (geometries ÷S, V unchanged, doping ×S2): C'ox=S·Cox, β'=S·β, I'D=S·ID (current rises because V not scaled while device gets stronger). P'=S·P, A'=A/S2 → P'/A'=S3·P/A — cubic blowup. Chip would melt; hence industry moved to constant-field (full) scaling where voltage scales with geometry.

Part B Answers

  1. (a) 3-nFET series, all VG=3.3V, VG−VTn=2.70V: M1: Vout,M1=Min[3.3,2.7]=2.70V. M2 sees Vin=2.70V → Min[2.70,2.7]=2.70V. M3 same → 2.70V. Only the first transistor imposes the threshold drop; the degraded value is already ≤VG−VTn for the following FETs, so they pass it unchanged (common trap is to subtract VTn at every stage → 1.5V,2.1V etc. — wrong).

    (b) Cascaded gate: Node A = output of M1 =2.70V = VG2. For M2, VG2−VTn=2.70−0.60=2.10V. If M2 drain =3.3V → Vout2=Min[3.3,2.10]=2.10V (second threshold loss — cascaded loss, now two VTn drops from VDD: 3.3−0.6−0.6=2.1V). If M2 drain =0V → Vout2=Min[0,2.10]=0V (strong 0) — nFET passes 0 with no loss.

    (c) Mixed node Vx: pFET: higher-voltage terminal is source → source=VDD=3.3V, drain=Vx, VSGp=VS−VG=3.3−3.3=0 ≤|VTp| → OFF. nFET: lower-voltage terminal is source → source=GND=0V, drain=Vx, VGSn=0−0=0 ≤VTn → OFF. Both OFF → Vx=floating / high-Z (undefined), not driven to either rail. If pFET gate is 0V instead: VSGp=3.3V ≥0.6V → ON, Vx=Max[VGp+|VTp|, Vin]=Max[0.6,0?]= but source is VDD, so pFET passes strong 1: Vx=3.3V (and nFET if its gate also went high would be contention — CMOS forbids both ON to same node).

  2. (a) K-map: 3-var map (a rows, bc columns). Minterms 1(001),2(010),5(101),6(110) are 1s; 0(000),3(011) are X. Group 0-1-2-3 forms a 4-group covering a'=0 (b'c + b'c' + bc' + bc terms) but with X, the prime implicants are: group (0,1,2,3) is not all covered? Minimal cover is two 2-groups: (0,1) + (2,3) etc. Espresso gives f = b'c + b·c' = b⊕c. The 4-group a' is not prime because adding minterms 5,6 breaks it; the actual primes are b'c (covers 1,5) and bc' (covers 2,6) using don't cares 0,3 to enlarge. Variable a is eliminated — the function is independent of a (output depends only on b,c). Many students include a — trap.

    (b) Complement: f = b'c + bc' → f' = (b'c + bc')' = (b + c')·(b' + c) = b·c + b'·c' (XNOR). Expand to SOP: f' = b c + b'c'. Literals in f' = 4 (b,c,b',c') → 4 NMOS + 4 PMOS = 8 transistors for the core gate (assuming b',c' available). If complemented inputs must be generated: +2 inverters (4T) → 12T total. Consistent with faculty 8T XOR/XNOR count with rail reuse.

    (c) PDN from f' = b c + b'c': OR of two AND terms → two parallel branches to GND: Branch1: nFET b in series with nFET c; Branch2: nFET b' in series with nFET c'. PUN dual: series↔parallel → two series groups between VDD and OUT: Group1 (b ∥ c) in series with Group2 (b' ∥ c'). Gate labels unchanged. Verify: PDN conducts when (b∧c)∨(b'∧c') → f'=1 → f=0; PUN conducts when (b∨c)∧(b'∨c') → f=1 — dual and complementary.

  3. (a) Squares: nstraight=l/w=180/0.6=300 squares. ncorner=4 → 0.635 each (current crowding at outside of bend makes corner less resistive than a full square) → ncorner,eff=4×0.635=2.54. Total n=300+2.54=302.54 squares. Rline=Rs·n=32×302.54=9681 Ω (≈9.68kΩ). If Rs=30, R≈9076Ω — same method.

    (b) Tox=7000 Å=7000×10−10m=7×10−7m. Cline=εox·w·l/Tox=3.9·8.854×10−12·0.6×10−6·180×10−6 /7×10−7 =34.53×10−12·108×10−12/7×10−7=5.33×10−15F =5.33 fF. τ=R·C=9681×5.33f=51.6×10−12s =51.6 ps (≈0.052 ns). With Rs=30 →48.4 ps.

    (c) Full scaling S=1.5: w'=w/S, l'=l/S, T'ox=Tox/S, Rs=ρ/t → t'=t/S → R's=Rs (ρ scales? Actually Rs unchanged to first order; number of squares n'=l'/w'=l/w=n → R'≈R). More precisely Rline≈Rs·n → R'≈R. C'line=εox·w'·l'/T'ox=ε·(w/S)(l/S)/(T/S)=C/S → C' = C/S. Hence τ' = R'·C' = τ/S (delay improves). For S=1.5, τ'=51.6/1.5=34.4 ps. This τ factor 1/S is not in the table — derived via R·C.

  4. (a) Topologies: F=(A·B+C·D)' → F' = A·B + C·D. Literals in F' =4 → 4 NMOS +4 PMOS =8T. PDN: (A ser B) ∥ (C ser D) between OUT–GND. PUN dual: (A ∥ B) ser (C ∥ D) between VDD–OUT.

    (b) Graphs: NMOS graph nodes {OUT, X1, X2, GND} edges: A:OUT–X1, B:X1–GND, C:OUT–X2, D:X2–GND. PMOS graph nodes {VDD, Y1, OUT} edges: A:VDD–Y1, B:VDD–Y1 (parallel), C:Y1–OUT, D:Y1–OUT (parallel).

    (c) Common Euler path: One valid trail is A → B → D → C (or A→C→D→B, B→A→C→D etc.). Check: NMOS: OUT–A–X1–B–GND–(jump?) Actually path A→B uses OUT–X1–GND, then needs to go to X2 via OUT? The Euler trail A–B–D–C corresponds to nodes OUT→X1→GND→X2→OUT — wait GND→X2 is edge D (X2–GND) reversed, X2→OUT is edge C. Similarly PMOS: VDD→Y1 via A, Y1→VDD via B (backtrack)?? A more standard published common path for AOI22 is A–C–D–B or B–A–C–D. Any of the 8 common trails is acceptable. Poly order becomes that sequence along a single diffusion run: diffusion strip crossed by poly gates in that order, shared diffusion between series devices, parallel branches share diffusion at both ends (or compact "+" cross). If no common path existed, layout would require a diffusion break / jog (two separate diffusion runs with metal strapping) — area and parasitics increase, not compact single-row stick.

  5. (a) Before scaling (S=1): Cox=2.878×10−7F/cm2=2.88 fF/µm2 (120Å). CG=Cox·W·L=2.88×9×0.6=15.54 fF. βn=k'n(W/L)=150×(9/0.6)=150×15=2.25 mA/V2. Rn=1/[βn(VDD−VTn)]=1/[2.25m×2.7]=164.6 Ω. IDn,sat=(β/2)(2.7)2=8.20 mA.

    (b) Full scaling S=1.5: Derivations: C'ox=εox/t'ox=ε/(t/S)=S·Cox → S. W'=W/S, L'=L/S → W'/L'=W/L unchanged. k'n=μnCox → k''=S·k' → β'=k''·W'/L'=S·β → β'/β=S. V'DD=VDD/S, V'T=VT/S → (V'−V'T)=(V−VT)/S. Hence R'n=1/[β'·(V'−V'T)]=1/[Sβ·(V−VT)/S]=1/[β(V−VT)]=R' = R (unchanged — trap is to answer R/S). C'G=C'ox·W'·L'=S·Cox·W·L/S2=CG/S → C'/C=1/S. Numerically: C'G=15.54/1.5=10.36 fF, R'n=164.6 Ω, β'=3.375 mA/V2, I'D=ID/S=5.47 mA. Untabulated τ=R·C: τ=164.6×15.54f=2.56 ps, τ'=164.6×10.36f=1.71 ps → τ'/τ=1/S=0.667. Power-delay product P·τ scales as (P/S2)·(τ/S)=Pτ/S3.

    (c) Constant-voltage scaling: Geometries ÷S but voltages unchanged. Then β'=S·β (same), but (V−VT) unchanged → R'n=1/[Sβ(V−VT)]=R/S=109.7 Ω. I'D=S·ID=12.30 mA (current rises). P'D=I'·V=S·P, Area'=A/S2 → P'/Area = S3·P/A — the table's S3 blowup, which is why constant-V scaling is unsustainable.

Part C Answers

  1. (a) Cox, γ: Cox=εox/tox=3.9·8.854×10−14 / (110×10−8)=3.453×10−14/1.1×10−6=3.139×10−7 F/cm2 =3.14 fF/µm2. εSi=11.8·ε0=1.0448×10−12 F/cm. γ=√(2q·εSi·Na)/Cox=√(2·1.602×10−19·1.045×10−12·9×1014)/3.139×10−7=√(3.013×10−16)/3.139×10−7=1.736×10−8/3.139×10−7=0.0553 V½ (with Na=8×1014 gives 0.0569 as in notes).

    (b) φF and VTn@2V: |φF|=(kT/q)ln(Na/ni)=0.026·ln(9×1014/1.45×1010)=0.026·ln(62069)=0.026·11.036=0.2869V → 2|φF|=0.5739V. VTn@2V =0.50+0.0553(√(0.5739+2)−√0.5739)=0.50+0.0553(1.6043−0.7576)=0.50+0.0553·0.8467=0.50+0.0468=0.547V.

    (c) At VSBn=3V: VTn=0.50+0.0553(√3.5739−0.7576)=0.50+0.0553(1.8905−0.7576)=0.50+0.0627=0.563V. VDSn,sat=VGSn−VTn=3.0−0.563=2.437V. Given VDSn=2.4V <2.437V → triode (linear) region. k'n=μnCox=530·3.139×10−7=1.664×10−4 A/V2=166.4 µA/V2. βn=k'n(W/L)=166.4×12=1996.5 µA/V2=1.997 mA/V2. IDn=β[(VGS−VT)VDS−VDS2/2]=1.997m·[2.437·2.4 −2.88]=1.997m·[5.8488−2.88]=1.997m·2.9688=5.93 mA. If saturation formula were misapplied, IDn,sat=(β/2)(2.437)2=0.998m·5.94=5.93 mA — numerically similar near the boundary but the region test is the marked trap. (With VDS=2.8V >Vsat the device would be saturated with the same 5.93 mA.)

  2. (a) β, region, ID: W/L=22/0.45=48.89. βn=135×48.89=6600 µA/V2=6.60 mA/V2. VDSn,sat=VGSn−VTn=3.3−0.65=2.65V. VDSn=3.3V ≥2.65V → saturation. IDn=(β/2)(2.65)2=3.30m·7.0225=23.17 mA.

    (b) Actual R: Rn,actual=VDSn/IDn=3.3/23.17m=142.4 Ω.

    (c) Linear model: Rn,lin=1/[βn(VDD−VTn)]=1/[6.60m·2.65]=1/17.49m=57.2 Ω (η=1). Ractual ≈2.49× Rlin — linear model underestimates resistance at this high-VDS saturated bias. Reason: η=1 formula is derived at operating point b (non-saturated, small VDS) where R=2/{β[2(VGS−VT)−VDS]} or point a R≈1/[β(VGS−VT)]; at point c (saturation) R=2VDS/[β(VGS−VT)2]=2·Rlin·VDS/(VGS−VT) >Rlin. Faculty's trap: students blindly use Rlin for saturated bias and get 57Ω vs true 142Ω.

    (d) Elmore (3-stage ladder, each R=57.2Ω, each C=32fF): TD=R1C1+(R1+R2)C2+(R1+R2+R3)C3=57.2·32f +114.4·32f +171.6·32f = (57.2+114.4+171.6)·32f =343.2·32f =10.98×10−12s =11.0 ps. For 2 stages: 57.2·32f +114.4·32f=5.49 ps. Using the FET RC example caps CD≈18.5fF, the same 3-stage gives 57.2·18.5f·6=6.35 ps. Any consistent Rlin·C product with correct Elmore sum is accepted.